The present invention relates, in general, to the field of integrated circuit dynamic random access memories (DRAM) and those devices incorporating embedded DRAM. More particularly, the present invention relates to a DRAM refresh period adjustment technique which is based on the retention time of one or more unused memory cell(s) having characteristics very similar to the characteristics of the memory cell(s) with the shortest retention time used in the DRAM array.
Among the advantages of DRAMs over static random access memory (SRAM) and other integrated circuit data storage technologies is that their structure is very simple in that each cell typically comprises but a single small capacitor and an associated pass transistor. However, since these capacitors are made very small to provide maximum memory density and they can, under the best of circumstances, only hold a charge for a short period of time, they must be continually refreshed.
In essence, the circuitry to effectuate this refresh operation then serves to effectively read the contents of every cell in a DRAM array and refresh each one with a fresh “charge” before the charge leaks off and the data state is lost. In general, this “refreshing” is done by reading and restoring every “row” in the memory array whereby the process of reading and restoring the contents of each memory cell capacitor re-establishes the charge, and hence, the data state.
Another aspect of DRAM memory, whether stand-alone or embedded is that the frequency with which the cell contents must be refreshed is a function of, among other factors, device temperature. At lower operating temperatures, the memory need not be refreshed as frequently as at higher temperatures. Since this refresh operation adds to the overall latency in memory accesses, the ability to accurately sense the then current operating temperature and adjust the refresh of the memory to the lowest possible rate is highly desirable given the need for ever quicker “reads” and “writes” to the memory.
Therefore, it is known to adjust the refresh period of a DRAM memory by changing the refresh period based upon the sensed temperature of the device. Among the limitations of current techniques is that an assumption of the retention time of the cells as a function of temperature must first be made. In addition the circuitry for monitoring this temperature must be extremely accurate. Known techniques also do not take into consideration any operational voltage variation contribution to the cell retention time.
Currently DRAM memory is used extensively in mobile, battery-powered applications such as personal digital assistants (PDAs), cellular telephones, notebook computers and the like. In these applications, the DRAM is generally written to or read from (i.e. “active”) for only a small portion of the time the device is powered up. When the DRAM array is not active, it is in standby mode. Nevertheless, the data in all or part of the DRAM must be retained even when in this standby mode. In order for this DRAM data to be retained, each data bit must be read and restored more frequently than the data retention time of the worst DRAM bit in the memory. This read and restore (or refresh) operation accounts for most of the power consumption of the DRAM in standby. It is therefore highly desirable to be able to adjust the refresh period to the maximum possible value for the DRAM under the DRAM's then current operational conditions in order to minimize power consumption.
Empirically, the retention time of DRAM bits typically fit a normal distribution and manufacturers of these chips generally utilize spare elements to replace anywhere from tens to thousands of the DRAM bits with the shortest refresh times. Since in this normal distribution it is the tail which is replaced, the replaced bits with the longest retention time will have characteristics very similar to the bits that were not replaced that have the shortest retention times. In this manner, the refresh period of the DRAM array is determined by the DRAM bit with the shortest retention time and the retention time of the replaced bits is not considered since the replaced bits are not ever written to or read from. It may be desirable to use this method only in standby or low-power modes of operation.